Sample rate converters are devices that are used to convert an input digital signal having a first, input, sample rate to an output digital signal having a different second, output, sample rate. They are common to many different fields of signal processing, including, but not limited to, communications and audio systems. For example, in audio systems and applications, the sample rate of a CD is 44.1 kHz; the sample rate of a digital audio tape (DAT) is typically 48 kHz. Clearly, if data is required to be transferred from CD to DAT, the sample rate must be converted such that the audio can be output at the correct frequency from the DAT, i.e. such that it does not sound “speeded up”.
Many different architectures are known for sample rate converters. One such architecture is an asynchronous sample rate converter 10 (ASRC), for example as shown in FIG. 1. The ASRC 10 has a rate estimator 12, which receives a clock signal from the first, input, sample-rate domain, and a clock signal from the second, output, sample-rate domain, and calculates a delay variable a on the basis of the two clock signals.
A polynomial interpolator 14 receives the delay variable α and calculates the output signal data samples (i.e. the data having a different sample rate) by interpolating between the input signal data samples using α. This aspect will be described in greater detail with respect to FIG. 3.
In the illustrated example, an upsampling filter 16 is used to upsample the input data such that the polynomial interpolator 14 is less complex. That is, by increasing the number of data points in the input data, the required accuracy of the interpolation is less, and a lower-order interpolator can be used. A downsampling filter 18 is then used to downsample the data output from the interpolator 14.
As a by-product of generating the delay variable a, the rate estimator 12 may also calculate a ratio of the input sample rate to the output sample rate. Such a ratio may be useful for other parts of the system in which the sample rate converter 10 is incorporated.
Thus it is desirable that the rate estimator 12 should converge as quickly as possible to the correct values of the frequency ratio and the delay variable α, such that the sample rate converter 10 can begin to output data as soon as possible after start up.
FIG. 2 is a graph illustrating the delay variable a used to calculate the output data.
In this illustrative example, an analogue input signal 30 has a smoothly varying amplitude over time. An input digital signal is generated by periodically sampling the analogue signal 30 at an input sample rate to obtain input samples (illustrated as solid lines in FIG. 2). In this example, the desired output samples (illustrated by dashed lines in FIG. 2) are synchronized with an output clock signal which has a higher frequency than the input clock signal. The delay variable a corresponds to the time difference between corresponding samples in the input data and the output data. More specifically, the delay variable a associated with each sample in the output data is the time difference between that sample and the previous sample in the input data. Thus, as the output sample rate is higher than the input sample rate, in FIG. 2, α starts at one and is then ramped down with each sample by an amount that is proportional to the difference between the input and output sample rates. When α becomes less than zero, the value of α wraps with modulo 1, and starts decreasing again from a value just less than one. At the point of wrapping, an additional output sample is generated.
It will be apparent to those skilled in the art that alternative definitions of a can be used without substantially affecting the operation of the converter. For example, α could be defined as being equal to zero initially before being increased to one (the normalized period of the input clock signal), and then wrapping back to zero.
The polynomial interpolator 14 comprises a buffer that is used to store the input data having an input sample rate FSI. FIG. 3 is an illustration of this buffer 20, which is depicted as a circle in the present case. The buffer 20 comprises a number of memory locations, or slots, 22, in which data samples are stored. A read pointer 24 points to a slot which contains data that is to be read out to the polynomial interpolator, and used to calculate a new data sample for the output data having an output sample rate FSO. Data is read out of the buffer 20 at the output sample rate FSO. A write pointer 26 points to a slot in which input data having the input sample rate FSI is to be written. Data is written to the buffer 20 at the input sample rate FSI.
Although the buffer 20 is depicted as a circle, it will be apparent to those skilled in the art that the buffer 20 may take a linear form, with the pointers 24, 26 cycling back to the first address of the buffer upon reaching the end address of the buffer.
Once the data has been read out of a particular slot 22, the data in that slot may be overwritten with new data. FSI and FSO are generally different, and thus there necessarily exist mechanisms for preventing the read pointer 24 from catching up with the write pointer 26 or vice versa. In the example illustrated in FIG. 2, the output sample rate is higher than the input sample rate. Thus, when a wraps around to one again (i.e. one extra output sample has been generated), the read pointer 24 reads a data sample from the same slot 22 twice. This compensates for the inherent frequency difference between the input sample rate FSI and the output sample rate FSO.
However, so-called clock “jitter”—short-term variation in the clock frequencies—may cause the write pointer 26 to catch up with the read pointer 24, or the read pointer 24 to catch up with the write pointer 26. In the former case, data would be overwritten that has not yet been read. In the latter, an entire buffer's worth of data samples would not be read. Either of these events would cause the sample rate converter 10 to malfunction.
If the rate estimator 12 is to be used to generate read and write pointers for the buffer, it is desirable that these never be equal to one another. That is, the read and write pointers should not point to the same data element in the buffer, causing the sample rate converter 10 to malfunction.
Further, as mentioned above, there may be a certain amount of jitter in the input clock signal, i.e. short-term variation in the clock frequency. It is desirable that the sample rate converter 10 should be resistant to such jitter, and continue to output stable values of α and the frequency ratio, and different values of the read and write pointers, regardless of the jitter in the input clock frequency.